http://www.springer.com/east/home/engineering/electronics?SGWID=5-191-22-173781598-detailsPage=ppmmediaaboutThisBookWafer Level 3-D ICs Process Technology
Series: Series on Integrated Circuits and Systems
Tan, Chuan Seng; Gutmann, Ronald J.; Reif, L. Rafael (Eds.)
2008, Approx. 420 p. 105 illus., Hardcover
ISBN: 978-0-387-76532-7
Due: June 2008
Table of contents
Overview of Wafer Level 3-D ICs.- Monolithic 3-D Integrated Circuits.- Stacked CMOS Technologies.- Wafer Bonding Technologies and Strategies for 3-D ICs.- Through Silicon Via Fabrication, Backgrind, and Handle Wafer Technologies.- Cu Wafer Bonding for 3-D ICs Applications.- Cu/Sn Solid-Liquid Interdiffusion Bonding.- An SOI-Based 3-D Circuit Integration Technology.- 3-D Fabrication Options for High Performance CMOS Technology.- 3-D Integration Based upon Dielectric Adhesive Bonding.- Direct Hybrid Bonding.- 3-D Memory.- Circuit Architectures for 3-D Integration.- Thermal Challenges of 3-D ICs.- Status and Outlook.
Overview of Wafer Level 3-D ICs.- Monolithic 3-D Integrated Circuits.- Stacked CMOS Technologies.- Wafer Bonding Technologies and Strategies for 3-D ICs.- Through Silicon Via Fabrication, Backgrind, and Handle Wafer Technologies.- Cu Wafer Bonding for 3-D ICs Applications.- Cu/Sn Solid-Liquid Interdiffusion Bonding.- An SOI-Based 3-D Circuit Integration Technology.- 3-D Fabrication Options for High Performance CMOS Technology.- 3-D Integration Based upon Dielectric Adhesive Bonding.- Direct Hybrid Bonding.- 3-D Memory.- Circuit Architectures for 3-D Integration.- Thermal Challenges of 3-D ICs.- Status and Outlook.
About this book
Wafer Level 3-D ICs Process Technology focuses on foundry-based process technology that enables the fabrication of 3-D ICs. The core of the book discusses alternative technology platforms for pre-packaging wafer level 3-D ICs, with an emphasis on wafer-to-wafer stacking. Driven by the need for improved performance, a number of companies, consortia and universities are researching methods to use short, monolithically-fabricated, vertical interconnections to replace the long interconnects found in 2-D ICs. Stacking disparate technologies to provide various combinations of densely-packed functions, such as logic, memory, MEMS, displays, RF, mixed-signal, sensors, and power delivery is potentially possible with 3-D heterogeneous integration, making this technology the "Holy Grail" of system integration.
Wafer Level 3-D ICs Process Technology focuses on foundry-based process technology that enables the fabrication of 3-D ICs. The core of the book discusses alternative technology platforms for pre-packaging wafer level 3-D ICs, with an emphasis on wafer-to-wafer stacking. Driven by the need for improved performance, a number of companies, consortia and universities are researching methods to use short, monolithically-fabricated, vertical interconnections to replace the long interconnects found in 2-D ICs. Stacking disparate technologies to provide various combinations of densely-packed functions, such as logic, memory, MEMS, displays, RF, mixed-signal, sensors, and power delivery is potentially possible with 3-D heterogeneous integration, making this technology the "Holy Grail" of system integration.
Wafer Level 3-D ICs Process Technology is an edited book based on chapters contributed by various experts in the fields of wafer-level 3-D ICs process technology and applications enabled by 3-D integration.
Written for:
Professionals and engineers in the field of 3-D ICs
Keywords:
Applications enabled by 3-D integration
Three-dimensional (3-D) integration
Through Silicon vias (TSVs)
Wafer bonding
Wafer-Level 3-D Technology Platforms
Applications enabled by 3-D integration
Three-dimensional (3-D) integration
Through Silicon vias (TSVs)
Wafer bonding
Wafer-Level 3-D Technology Platforms
Sunday, Jan 21, 2008, 2:38PM
1 comment:
Holy moly, now the world will know Dr Tan's brilliance.
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