US 7,307,003

United States Patent	7,307,003
Reif , et al.	December 11, 2007

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Method of forming a multi-layer semiconductor structure incorporating a processing handle member

Abstract

A method of forming a multi-layer semiconductor structure includes attaching a handle-member to a top surface of a first structure using a first interface. At least one region of a bottom surface of the first structure is etched to form at least a first via-hole for exposing a portion of a first conductive member defined on the first structure. A conductive material is disposed in the first via-hole such that a first end of the conductive material is in electrical communication with the first conductive member and a second end of the conductive material is exposed at the bottom surface of the first structure. A second interface is disposed over at least the second end of the conductive material, which serves as a bonding and/or electrical interface between the first conductive member defined on the first structure and a second structure of the multi-layer semiconductor device structure.

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Inventors:	Reif; Rafael (Newton, MA), Chen; Kuan-Neng (Cambridge, MA), Tan; Chuan Seng (Cambridge, MA), Fan; Andy (Cambridge, MA)
Assignee:	Massachusetts Institute of Technology (Cambridge, MA)
Appl. No.:	10/749,103
Filed:	December 30, 2003

Seminar at ITRI, Taiwan

Wafer Level 3-D Integration技術研討會
前 言：
為了滿足消費者對電子產品輕薄短小、高效能與多功能的需求，IC構裝已朝三度空間(3 Dimension)之技術發展，而以晶圓級製程(Wafer Level Processing)為基礎的3D整合技術更是日益重要。工研院『先進微系統與構裝技術聯盟;AMPA』有鑑於此，特別邀請新加坡南洋技術大學之Dr. Chuan Seng Tan於2月26日來台，針對晶圓級3D技術平台、製程與應用作詳細報導，內容深入淺出，歡迎從事系統組裝(SMT)、電路板、IC構裝、光電等產業或對此課程有興趣者報名參加！
時 間：97年2月26日（星期2）9:00至11:30
地 點：工研院9館010會議室 (新竹縣竹東鎮中興路四段195號，電話︰03-5918062)
主辦單位：工業技術研究院電子與光電研究所
協辦單位：先進微系統與構裝技術聯盟
講 師： Dr. Chuan Seng Tan, Research Fellow, Nanyang Technological University, Singapore
• Dr. Tan received his B.Eng. degree in electrical engineering from University of Malaya, Malaysia, in 1999. Subsequently, he completed his M.Eng. degree in advanced materials from the National University of Singapore under the Singapore-MIT Alliance (SMA) program in 2001.
• In the fall of 2001, he began his doctoral work at the Massachusetts Institute of Technology, Cambridge, USA, and was awarded a Ph.D. degree in electrical engineering in 2006.
• Currently he is a research fellow in Nanyang Technological University, Singapore, under the support of the Lee Kuan Yew Postdoctoral Fellowship.
• He is working on process technology of three-dimensional integrated circuits (3-D ICs). He co-edited a book entitled “Wafer Level 3-D ICs Process Technology,” scheduled to be published by Springer in June 2008.

參加對象：系統組裝(SMT)、電路板、IC構裝、光電等產業之工程師、主管與有興趣者
費 用：一般學員每人新台幣1,000元，微機電產業發展聯盟會員每人新台幣500元
先進微系統與構裝技術聯盟會員享有5名人員免費，第6人起每人新台幣500元(含稅、講義與茶點)。
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